Jaidev Patwardhan


My primary area of research is Computer Architecture. I am currently working on the Troika project that looks at future architectures built using non-silicon devices. In particular, we are looking at building an architecture using Carbon Nanotube FET's as the active devices. To assist in the assembly of these tiny devices, we plan to use a DNA as a scaffold. The Troika project is a joint venture between groups at Duke CS, Chemistry, Physics as well as at UNC-Chapel Hill and NCSU.

I have also worked on analyzing the CPU profile of commercial workloads, with the aim of evaluating the benefits of protocol offload. This was an extension to work I did when I interned with the DPG-CPU Architecture group in Intel at Hillsboro, Or in summer 2002. While I was there, I looked at the overhead due to the linux protocol stack when running some microbenchmarks. This work led to a paper published at ISPASS '03.

Before interning at Intel, I was involved in research on large instruction windows. We showed that caching instructions that depended on long latency operations like cache misses could free up space in the issue queues for other ready instructions to execute. For our set of spec cpu 2000 benchmarks, we achieved a significant speedup. For more details, refer to our paper that appeared in ISCA 2002. As an extension to this paper, I evaluated different register file architectures to support large windows. My simulations showed that a multi-banked register file architecture outperformed a hierarchical register file.

In my first year, I was part of a team project as part of the Ubiquitous Computing course which led to a workshop publication. In that work, we examined the benefits of using continuous consistency in portals aimed at wireless devices. We found that we could achieve significant savings in energy if we used continuous consistency metrics to reduce the amount of data transferred between the portal and the wireless device. You can find more details in the paper.